An Ultra-Low Latency Hardwired User-Space Interrupt Handler for Hardware Accelerators

Heterogeneous SoCs enhance system performance across various applications. However, managing and integrating components, interfacing hardware and software, and overseeing shared resources pose significant challenges for these promising systems. Accelerators, as critical resources within SoCs, require signals and interrupts to communicate effectively with the rest of the system, particularly host processors. Interrupt-based interfaces are the most traditional method for synchronizing accelerators with processors; for instance, an accelerator will notify a processor upon job completion. Context switching to invoke the corresponding Interrupt Service Routine (ISR), along with toggling between user mode and kernel mode, represents the minimum prerequisites imposed on the system. These complex OS interventions for interrupt handling in accelerator-processor communication markedly degrade system performance. In this paper, we introduce a lightweight hardwired interrupt handler designed for user-space management of accelerators interacting with processors. The key component of this handler is an innovative hardware-level function call that activates upon the arrival of interrupts, facilitating the processing of accelerator requests. This approach contrasts with existing process-level programmed function calls, which rely on explicit execution of jump instructions, and OS-managed kernel-mode ISR invocation. With a minor modification in the processor control path, the proposed interrupt handler operates in user space without necessitating context switching or OS intervention. According to evaluation results, the proposed handler reduces the interval between interrupt occurrence and handling from hundreds of clock cycles to less than 5 cycles, resulting in up to 4.75x performance enhancement with negligible area overhead.