Design Methodology of an Inductorless GaAs pHEMT SPDT Switch With Compact Size for Sub-6 GHz Applications

This paper presents an inductorless design methodology for compact single-pole double-throw (SPDT) switches in Sub-6 GHz applications. To achieve compactness and meet key performance metrics below 5.0 GHz, the methodology focuses on optimizing the trade-off between on-resistance and parasitic capacitance by controlling the gate width of the transistors. Based on this analysis, design parameters are derived to ensure low insertion loss and high isolation. The proposed switch is implemented using a dual-gate pHEMT in a 500-nm GaAs BiFET process. Measurement results demonstrate good agreement with simulations, confirming the validity of the design approach. The fabricated switch operates from DC to 5.0 GHz, exhibiting a return loss greater than 14.6 dB, insertion loss less than 0.296 dB, and isolation exceeding 31.6 dB. Additionally, a measured input 1-dB compression point (P<inline-formula> <tex-math notation="LaTeX">${}_{1dB}$ </tex-math></inline-formula>) of 32.0 dBm at 4.0 GHz verifies its high power-handling capability. The inductorless design enables a compact chip size of <inline-formula> <tex-math notation="LaTeX">$910\times 570~\mu $ </tex-math></inline-formula>m2, making it well-suited for integrated RF front-end applications in the Sub-6 GHz band.