An energy-efficient Flash-SAR ADC with two-step flash structure in a 0.18 μm CMOS process

Abstract With the increasing performance requirements for data acquisition in applications such as the Internet of things and artificial intelligence, analog-to-digital converters (ADCs) face stringent trade-offs among speed, resolution, and power consumption. This paper presents an 8 bit ADC employing a two-step Flash-SAR hybrid architecture. The Flash-SAR architecture can effectively balance power consumption and speed, making it suitable for low-power, high-speed application scenarios. The innovation of this architecture lies primarily in the use of a two-step structure at the front end. By dividing the comparison process into two stages, the number of comparators in the 4-bit Flash ADC at the front end is reduced to 6, while employing a comparator based on a floating inverter amplifier (FIA), which significantly reduces both power consumption and area. Another innovation is that the comparison process in the two division stages is independent, allowing the use of shared FIA capacitor technology to achieve area reduction. Another innovation is that the back end adopts a VCM-based SAR architecture and uses a double-tail dynamic comparator with two-stage preamplification to suppress offset and kickback noise while maintaining high speed. The circuit is evaluated in a 0.18 μm CMOS process, operates from a 1.8 V supply, and achieves a sampling rate of 100 MS/s. Presimulation results show that the proposed ADC achieves a maximum DNL of + 0.5 LSB, a maximum INL of − 0.8 LSB, an ENOB of 7.64 bits, and a total power consumption of 4.244 mW. Compared to previous work, this architecture offers approximately 1 bit higher precision than a Flash structure with the same resolution, significantly increases the sampling rate by 2500× compared to a pure SAR, and improves the Figure of Merit (FOM) by nearly 10×.