Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA

This paper presents step skipping acceleration techniques for a class of convergence algorithms computing arithmetic functions. In particular, an extension of the fast adder carry-skip procedure is carried out for special purpose cellular array circuits implementing iterative logical functions for which some propagating information may be fruitfully computed ahead of the current step output computation. This information is thus carried to the next stage, accelerating the overall calculation. An application is given for the 2´s complement sign changing circuit, then for the step-skipping acceleration circuits used in the implementation of the ln(x) convergence algorithm. FPGA implementations on Xilinx Virtex IV have been achieved with comparative analysis of 32- to 512-bit computing algorithms. Workshop de Arquitecturas, Redes y Sistemas Operativos (WARSO) Red de Universidades con Carreras en Informática (RedUNCI)