An improved convergence algorithm to compute ln(x) – FPGA implementations

This paper presents FPGA implementations of classical algorithms for computing ln(x) with some improvement at the level of the multiplication steps, and step skipping techniques. One starts from a practical implementation of ln(x) computation using a convergence method. The function is approximated by a multiplicative normalization technique, however, thanks to the peculiarity of the multiplicative factor, namely (1 + ai .2-i ), with ai ∈ {-1, 0, 1}, the successive multiplications have been replaced by additions. Doing so, one saves the use of LUT’s and eventually reduces processing time, as addition is generally faster than multiplication. Further, the acceleration technique, based on skipping trivial steps, improves performances. Implementations for FPGA are presented with time and slice cost evaluations. The Xilinx Virtex IV has been used for comparative analysis of 8 to 64-bit logarithm computing devices. II Workshop de Arquitecturas, Redes y Sistemas Operativos Red de Universidades con Carreras en Informática (RedUNCI)