Selection of the optimum stage number in pipelined floating-point units

In this work the pipeline theory applied to computing systems is reviewed. The effects of the stage delay, overhead stage delay, equalization factor and number of stages on the pipeline system performance are analyzed. A pipeline design method to identify the optimum number of stages is proposed. This method makes use of a trade-off expression that considers speed factor and hardware cost. The procedure is applied to turn a sequential Floating Point Unit (FPU) into a Pipelined Floating Point Unit (PFPU) capable to achieve a performance 600% larger. The effect of the physical limits on the PFPU maximum performance is analyzed. Eje: Arquitectura, Redes y Sistemas Operativos (ARSO) Red de Universidades con Carreras en Informática (RedUNCI)