Back to results
Bibliographic record · Consultation and access
Artículo

Design and Analysis of an Energy-Efficient Voltage Level Shifter for Low-Power Applications

Pulyala Vasundhara et al · Sumy State University · 2026

Supplementary material available
Quick overview. Review the resource’s basic details, then access the content using the main button. This page shows only the information needed to identify, cite, and open the work.

Resource access

Open the content from the main option or choose another available source.

DOAJ DOAJ Articles
Entrar por DOAJ
Main access

Supplementary material available

El enlace apunta a material asociado, anexos, tablas, datos o página complementaria. No se marca como libro/texto completo.
Open material

Summary

Descripción general del contenido del recurso.

This describes a low-energy voltage level shifter (LS) architecture. We further introduce a regulated cross-coupled (RCC) pull-up network to achieve a considerable reduction in dynamic power consumption with higher switching speed. The suggested LS can switch very low voltage signals below the input MOS device threshold up to the nominal supply voltage. A fast and very low power voltage level shifter (LS) is presented. By using a new regulated cross coupled (RCC) pull-up network, the switching speed is boosted and the dynamic power consumption is highly reduced. The proposed LS has the ability to convert input signals with voltage levels much lower than the threshold voltage of an MOS device to higher nominal supply voltage levels. The presented LS occupies a small silicon area owing to its very low number of elements and is ultra-low-power, making it suitable for low-power applications such as implantable medical devices and wireless sensor networks. Results of the post-layout simulation in a standard CMOS technology This LS is particularly appealing for low-power application fields, including implanted medical devices and wireless sensor networks, as it makes very little use of components and dissipation has been minimized. Benefiting from the use of sub-1V CMOS technology, it can convert as low input voltage level as 80 mV according to the post-layout simulation results. This LS gives the power dissipation of 123.1 nW with 23.7 ns propagation delay at supply voltages of 0.4/1.8 V (Low/High) and of input frequency of 1 MHz.

How to cite

Elegí el formato que necesitás y copiá la referencia al portapapeles.

APA 7

al, P. V. E. (2026). Design and Analysis of an Energy-Efficient Voltage Level Shifter for Low-Power Applications. https://doi.org/10.21272/jnep.18(1).01020

MLA

al, Pulyala Vasundhara et. "Design and Analysis of an Energy-Efficient Voltage Level Shifter for Low-Power Applications." 2026. https://doi.org/10.21272/jnep.18(1).01020.

Chicago

al, Pulyala Vasundhara et. 2026. "Design and Analysis of an Energy-Efficient Voltage Level Shifter for Low-Power Applications.". https://doi.org/10.21272/jnep.18(1).01020.

Harvard

al, P. V. E. 2026, Design and Analysis of an Energy-Efficient Voltage Level Shifter for Low-Power Applications, Sumy State University, available at: https://doi.org/10.21272/jnep.18(1).01020 [Accessed 7 Aug. 2026].

Share and print

Save the record, copy its permanent link, or print it as a PDF.

Export reference

You can export the record in common formats for use in a reference manager.

Resource details

Bibliographic information to help confirm that this is the correct material.

Title
Design and Analysis of an Energy-Efficient Voltage Level Shifter for Low-Power Applications
Author / contributors
Pulyala Vasundhara et al
Publisher
Sumy State University
Publication year
2026
ISSN
2077-6772
ISSN
2077-6772
Language
English

Subjects

Explore related resources through these subjects.

Copied