Development of Compact, Low-Power CMOS Toggle Flip-Flops for High-Speed Applications

A New True single-phase clock transistor using T flipflop (TSPC-T) is introduced to operate efficiently at low supply voltages (VDD) while ensuring high speed and reliability. T Flip-flop significantly minimizes unnecessary power consumption by disabling clock signals when they are unnecessary. The present flip-flop design has two different designs, i.e., Static Toggle Flip-Flop (STFF) design and Modified Clocked CMOS design (M-C2MOS). STFF is used to reduce the power consumption, by 0.08412 W, which is energy-efficient and better than designs like S2CFF (0.11621 W) and TGFF (0.1736 W), whereas M-C2MOS is used to minimize the PDP by (0.7746 fJ), outperforming existing designs like TGFF (3.0537 fJ) and S2CFF (1.0214 fJ). It reduces redundant transitions in the circuit while enhancing overall energy efficiency. Additionally, updating the flip-flop operation lowers the required devices and decreases power usage. In the present work, a comparative analysis of five existing flip-flop designs (TGFF, C2MOS, S2CFF, 18TSPC, 18TSPC_T) and the proposed design (STFF, M-C2MOS) is made. The proposed design (STFF, M-C2MOS) has better power and delay when compared to existing high-speed flip-flops. The design and analysis are carried out by using 32 nm CMOS technology. Simulation results demonstrate that the STFF design significantly improves energy efficiency, with a 10.3% reduction in power consumption at 1 V. These results highlight the importance of STFF and M-C2MOS in optimizing both power and speed, making them highly effective for modern low-power, high-performance digital applications.