Multi-Split SOI Super-Junction VDMOS: A TCAD Simulation Study of the Single-Event Effect

This work presents a radiation-hardened Superjunction Vertical Double-Diffused MOSFET (SJ-VDMOS) architecture designed to improve robustness against destructive single-event effects (SEEs), specifically Single-Event Gate Rupture (SEGR) and Single-Event Burnout (SEB). The proposed structure integrates a high-k gate dielectric stack based on silicon nitride, a graded N-type buffer layer, and a multi-split silicon-on-insulator (MS-SOI) buried oxide (BOX) embedded within the drift region. Two-dimensional TCAD simulations, calibrated with established physical models, are employed to investigate SEE behavior under vertical, lateral, and diagonal heavy-ion irradiation conditions. Simulation results demonstrate that the combined structural modifications effectively suppress parasitic bipolar transistor activation, reduce charge accumulation near the gate dielectric, and limit substrate hole injection by redistributing and neutralizing carriers within the critical regions of the device. As a result, the proposed SJ-VDMOS exhibits a significant expansion of the safe operating area, achieving up to a 50% improvement in SEGR survivability. In addition, the SEB tolerance is enhanced to approximately 55% of the rated breakdown voltage under a constant heavy-ion linear energy transfer (LET) of 89 MeV<inline-formula> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>cm2/mg. Importantly, these radiation-hardening benefits are obtained with minimal impact on the device&#x2019;s baseline electrical characteristics. The proposed structure provides an effective, design-oriented approach for simultaneous mitigation of SEGR and SEB, making it well-suited for space and high-radiation power electronics applications.