Enhanced Level Shifted Carrier-Based PWM Technique for Improving the Performance of T-Type NPC Inverters

The use of neutral point clamped (NPC) multilevel inverters has significantly increased in recent decades, due to their appealing features compared to two-level voltage source inverters. In many industry-level applications, they suffer from high harmonic distortion, power loss, junction temperature of the semiconductor switches and dc-link capacitor voltage imbalance issues which are largely dependent on the switching pulse width modulation (PWM) technique used. This work presents a sub-flattened triangular carrier-based pulse width modulation (PWM) technique, which can mitigate the aforementioned issues. The proposed PWM technique is a combination of the modulating signal of existing third-harmonic injected PWM (THPWM) and a newly shaped, sub-flattened, modified triangular carrier signal. The carrier signal introduces a flattened region, which modifies the switching sequences of the power switches. This modification significantly affects the harmonic profile, charging and discharging time of the dc-link capacitors, the total power loss, switch junction temperature and efficiency of the inverter. A three-phase grid-connected T-type NPC inverter is considered to evaluate the performance of the proposed PWM technique. An extensive comparative performance analysis of the proposed PWM technique has been carried out against existing PWM methods. The evaluation considers key performance indicators, including inverter PWM voltage harmonic profile, dc-link capacitor voltage balancing, power losses, junction temperature of the switches, and overall inverter efficiency. Simulations have been conducted using MATLAB/Simulink and PLECS platforms. Furthermore, a reduced-scale laboratory prototype has been developed and experimentally validated to support the simulation results.