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Memory disambiguation hardware: a review

Castro, Fernando et al · SEDICI UNLP · 2008

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Author / responsible party
Castro, Fernando et al
Publisher
SEDICI UNLP
Year
2008
Language
English

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One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions. Facultad de Informática

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APA 7

Castro, F. E. A. (2008). Memory disambiguation hardware: a review. http://sedici.unlp.edu.ar/handle/10915/9636

MLA

Castro, Fernando et al. "Memory disambiguation hardware: a review." 2008. http://sedici.unlp.edu.ar/handle/10915/9636.

Chicago

Castro, Fernando et al. 2008. "Memory disambiguation hardware: a review.". http://sedici.unlp.edu.ar/handle/10915/9636.

Harvard

Castro, F. E. A. 2008, Memory disambiguation hardware: a review, SEDICI UNLP, available at: http://sedici.unlp.edu.ar/handle/10915/9636 [Accessed 8 Aug. 2026].

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Title
Memory disambiguation hardware: a review
Author / contributors
Castro, Fernando et al
Publisher
SEDICI UNLP
Publication year
2008
Language
English

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Ciencias Informáticas; Filtering; LSQ; memory disambiguation; energy-efficiency
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