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Scheme Topological Modeling of Converters Signal Levels for Analytical Microsystems-on-Chip

V. V. Dovgiy et al · Vasyl Stefanyk Carpathian National University · 2016

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Author / responsible party
V. V. Dovgiy et al
Publisher
Vasyl Stefanyk Carpathian National University
Year
2016
ISSN
1729-4428
ISSN
1729-4428
Language
English

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The results of scheme-topology design and computer modeling for signal level converter of integrated circuits and micro analysis on the basic matrix chip (BMK) with the structures "silicon-on-insulator" (SOI) are present in paper

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APA 7

al, V. V. D. E. (2016). Scheme Topological Modeling of Converters Signal Levels for Analytical Microsystems-on-Chip. https://doi.org/10.15330/pcss.16.2.403-407

MLA

al, V. V. Dovgiy et. "Scheme Topological Modeling of Converters Signal Levels for Analytical Microsystems-on-Chip." 2016. https://doi.org/10.15330/pcss.16.2.403-407.

Chicago

al, V. V. Dovgiy et. 2016. "Scheme Topological Modeling of Converters Signal Levels for Analytical Microsystems-on-Chip.". https://doi.org/10.15330/pcss.16.2.403-407.

Harvard

al, V. V. D. E. 2016, Scheme Topological Modeling of Converters Signal Levels for Analytical Microsystems-on-Chip, Vasyl Stefanyk Carpathian National University, available at: https://doi.org/10.15330/pcss.16.2.403-407 [Accessed 8 Aug. 2026].

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Title
Scheme Topological Modeling of Converters Signal Levels for Analytical Microsystems-on-Chip
Author / contributors
V. V. Dovgiy et al
Publisher
Vasyl Stefanyk Carpathian National University
Publication year
2016
ISSN
1729-4428
ISSN
1729-4428
Language
English
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