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Selection of the optimum stage number in pipelined floating-point units

Balliriain, Eduardo et al · SEDICI UNLP · 2003

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Author / responsible party
Balliriain, Eduardo et al
Publisher
SEDICI UNLP
Year
2003
Language
English

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In this work the pipeline theory applied to computing systems is reviewed. The effects of the stage delay, overhead stage delay, equalization factor and number of stages on the pipeline system performance are analyzed. A pipeline design method to identify the optimum number of stages is proposed. This method makes use of a trade-off expression that considers speed factor and hardware cost. The procedure is applied to turn a sequential Floating Point Unit (FPU) into a Pipelined Floating Point Unit (PFPU) capable to achieve a performance 600% larger. The effect of the physical limits on the PFPU maximum performance is analyzed. Eje: Arquitectura, Redes y Sistemas Operativos (ARSO) Red de Universidades con Carreras en Informática (RedUNCI)

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APA 7

Balliriain, E. E. A. (2003). Selection of the optimum stage number in pipelined floating-point units. SEDICI UNLP. http://sedici.unlp.edu.ar/handle/10915/22723

MLA

Balliriain, Eduardo et al. Selection of the optimum stage number in pipelined floating-point units. SEDICI UNLP, 2003. http://sedici.unlp.edu.ar/handle/10915/22723.

Chicago

Balliriain, Eduardo et al. 2003. Selection of the optimum stage number in pipelined floating-point units. SEDICI UNLP. http://sedici.unlp.edu.ar/handle/10915/22723.

Harvard

Balliriain, E. E. A. 2003, Selection of the optimum stage number in pipelined floating-point units, SEDICI UNLP, available at: http://sedici.unlp.edu.ar/handle/10915/22723 [Accessed 8 Aug. 2026].

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Title
Selection of the optimum stage number in pipelined floating-point units
Author / contributors
Balliriain, Eduardo et al
Publisher
SEDICI UNLP
Publication year
2003
Language
English

Subjects

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Ciencias Informáticas; Optimum Stage Number; Pipelined Floating-Point Units; Architectures; sistema operativo; Optimization
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